Memory array apparatus with reduced data accessing time and method for the same

ABSTRACT

A memory array apparatus with shorter data accessing time is proposed. The memory array apparatus comprises a register administrator and a plurality of data registers between a micro controller and at least one memory array. The data to be accessed are divided into a plurality of data blocks according to a predetermined data unit. The data block is firstly stored in corresponding data register and then read by the main frame or stored into the corresponding memory array. At the same time, the next data block is stored in the corresponding data register through circuit switched by the micro controller. The pending time of the main frame and the data accessing time can be advantageously reduced.

FIELD OF THE INVENTION

[0001] The present invention relates to a memory array apparatus,especially to a memory array apparatus with shorter data accessing timeto reduce waiting of a main frame, and method for the same.

BACKGROUND OF THE INVENTION

[0002] The flash memory has the advantages of compact size, low powerconsumption, shock resistance and non-volatility, and is suitable forportable electronic devices such as personal communication apparatus andpalm computer.

[0003]FIG. 1 shows a conventional flash memory array apparatus, whichmainly comprises an interface controller 13, a micro-controller 15, adata register 17, a data input/output port 18 and a flash memory array19. The interface controller 13 of the flash memory array apparatus isconnected to a main frame 10 through a bus 11. When data is to be storedinto the flash memory array 19, the main frame 10 commands themicro-controller 15 to divide the data to be stored into a plurality ofdata blocks according to a predetermined data unit such as 512 bytes.Each data block is firstly stored in the data register 17 and thenstored into the flash memory array 19 through the data input/output port18. On the contrary, the data transmission path is reversed when thedata is to be read.

[0004] However, in above-mentioned flash memory array apparatus, thedata transmission speed between the data register 17 and the flashmemory array 19 is relatively low. Moreover, the above-mentioned flashmemory array apparatus is designed to have single data register 17 andsingle flash memory array 19, the main frame 10 requires a waiting timebefore the data transmission between the data register 17 and the flashmemory array 19 is completed. The data accessing speed is notsatisfactory.

SUMMARY OF THE INVENTION

[0005] It is the object of the present invention to provide a memoryarray apparatus with shorter data accessing time to reduce waiting of amain frame, and method for the same.

[0006] In one aspect of the present invention, the data to be accessedis divided into a plurality of data blocks and a plurality of dataregisters are used to store temporarily the separate data block. Thedata accessing time between the memory array and the data register isexploited to the data transmission for the next data block, whereby thewaiting time of main frame can be reduced.

[0007] The various objects and advantages of the present invention willbe more readily understood from the following detailed description whenread in conjunction with the appended drawing, in which:

BRIEF DESCRIPTION OF DRAWINGS

[0008]FIG. 1 shows the block diagram of a conventional flash memoryarray apparatus.

[0009]FIG. 2 shows the block diagram of a preferred embodiment of thepresent invention.

[0010]FIG. 3 shows the storing flowchart of the preferred embodiment inFIG. 2.

[0011]FIG. 4 shows the timing diagram of the preferred embodiment inFIG. 2.

[0012]FIG. 5 shows the reading flowchart of the preferred embodiment inFIG. 2.

[0013]FIG. 6 shows the block diagram of another preferred embodiment ofthe present invention.

[0014]FIG. 7 shows the timing diagram of the preferred embodiment inFIG. 6.

DETAILED DESCRIPTION OF THE INVENTION

[0015]FIG. 2 shows a block diagram of a preferred embodiment of thepresent invention. The memory array apparatus of the present inventionmainly comprises an interface controller 23, a micro-controller 25, aregister administrator 30, a first data register 271, a second dataregister 272, a first data I/O port 281, a second data I/O port 282, afirst memory array 291 and a second memory array 292. The interfacecontroller 23 is connected to a main frame 20 through a main bus 21 andis also connected to the micro-controller 25. The register administrator30 has at least one bus switch 31, which is connected to the main frame20 through the main bus and connected to the micro-controller 25. Thebus switch 31 is controlled by the micro-controller 25 to selectivelycommunicate with one of the two data registers 271 and 272. The data I/Oports 281 and 282 are connected to the data registers 271 and 272,respectively, and corresponding memory arrays 291 and 292.

[0016]FIGS. 2 and 3 show the flowchart of the present invention. Thestoring process for main frame 20 to store data into the memory arrays291 and 292 comprises following steps:

[0017] Step 301: The main frame 20 informs the micro-controller 25 ofstoring operation through the main bus 21 and the interface controller23.

[0018] Step 302: The bus switch 31 of the register administrator 30 iscontrolled by the micro-controller 25 and selectively switched to afirst circuit 3171 connected with the first data register 271.

[0019] Step 303: The micro-controller 25 divides the data to be storedinto a plurality of data blocks with a predetermined data unit. In thepresent embodiment, the data unit is in terms of logical array block(LAB; 512 bytes). The plurality of data blocks contains a first datablock stored temporarily in the first data register 271. The first datablock belongs to an N data block series. The capacity of all dataregisters is larger than or equal to 512 bytes. Afterward, steps 304 and314 are simultaneously executed after the temporary storing process.

[0020] Step 304: The first data register 271 is controlled by themicro-controller 25 to store the first data block (N data block) intothe memory array 291 through the first data I/O port 281. The memory ischaracterized by a relative long accessing time. Therefore, themicro-controller 25 executes the step 314 simultaneous with the step304.

[0021] Step 314: The bus switch 31 of the register administrator 30 iscontrolled by the micro-controller 25 and selectively switched to asecond circuit 3172 connected with the second data register 272. Thesecond data block (N+1 data block) of the data blocks from the mainframe 20 is stored temporarily in the second data register 272.

[0022] Step 305: Whether the data stored in the first data register 271is completely stored in the memory array 291? If true, the steps 306 and316 are simultaneously executed.

[0023] Step 306: Due to the relative long accessing time of the memory,the second data block (N+1 data block) of the data blocks has beenstored temporarily in the second data register 272. At this time, thesecond data block (N+1 data block) of the data blocks stored temporarilyin the second data register 272 is moved to the second memory array 292through the second data I/O port 282.

[0024] Step 316: Simultaneously with the step 306, the bus switch 31 iscontrolled by the micro-controller 25 and again switched to the firstcircuit 3171 connected with the first data register 271. The next firstdata block (N data block) is stored into the first data register 271.

[0025] Step 307: Whether the data stored in the second data register 272is completely stored in the memory array 292. The steps 304 to 307 arerepeatedly executed until all data are stored into the memory array.

[0026]FIG. 4 shows the timing diagram of this embodiment. The tablecontents in row direction represent the data register and the tablecontents in column direction represent processing period.

[0027] In first phase, the main frame 20 sends the first data block tothe first data register 271, and the operation is symbolized by H→1B. Atthis time, the second data register 272 is idle.

[0028] In second phase, the first data block is moved from the firstdata register 271 to the memory array 291 and the operation issymbolized by 1B→1M. At this time, the main frame 20 sends the seconddata block to the second data register 272, and the operation issymbolized by H→2B.

[0029] In third phase, the second data block is moved from the seconddata register 272 to the second memory array 292, and this operation issymbolized by 2B→2M. At this time, the main frame 20 sends the nextfirst data block to the first data register 271, and the operation issymbolized by H→1B.

[0030] In fourth phase, the first data block is moved from the firstdata register 271 to the first memory array 291 and the operation issymbolized by 1B→1M. At this time, the main frame 20 sends the seconddata block to the second data register 272, and the operation issymbolized by H→2B. The operation in this phase is similar to theoperation in the second phase. In other word, the operations in thesecond and third phases are alternatively executed until all data arestored.

[0031] As can be seen from FIG. 4, the main frame 20 has no idle time inall phase of operation; the efficiency thereof can be fully exploited.

[0032]FIG. 5 shows the flowchart of reading operation.

[0033] Step 501: the main frame 20 informs the micro-controller 25 ofreading operation from the first memory array 291 and the second memoryarray 292.

[0034] Step 502: The first data block is moved from the first memoryarray 291 to the first data register 271.

[0035] Step 503: The bus switch 31 of the register administrator 30 iscontrolled by the micro-controller 25 and selectively switched to afirst circuit 3171 connected with the first data register 271.

[0036] Step 513: Simultaneously with the step 503, the second data blockis moved from the second memory array 292 to the second data register272. Afterward, a step 505 is executed.

[0037] Step 504: The main frame 20 reads the first data block stored inthe first data register 271 through the first circuit 3171.

[0038] Step 505: Waiting and detecting whether the second data block iscompletely stored in the second data register 272.

[0039] Step 506: The bus switch 31 of the register administrator 30 iscontrolled by the micro-controller 25 and selectively switched to asecond circuit 3172 connected with the second data register 272.

[0040] Step 517: Simultaneously with the step 507, the next first datablock is moved from the first memory array 291 to the first dataregister 271.

[0041] Step 508: Waiting and detecting whether the next first data blockis completely stored in the first data register 271. Afterward, steps503 to 508 are repeatedly executed until all data are read by the mainframe 20.

[0042]FIG. 6 shows the block diagram of another preferred embodiment ofthe present invention. The first preferred embodiment of the presentinvention is exemplified with two data registers 271 and 272, and twomemory arrays 29 land 292. However, the number of the data registers isnot necessarily matched with the number of the memory arrays. In thesecond preferred embodiment of the present invention, the memory arrayapparatus has three data registers 271, 272 and 273, which are used withtwo I/O ports 281 and 282 and two memory arrays 291 and 292. To schedulethe data blocks in the three data registers 271, 272 and 273, theregister administrator 30 has a first I/O switch 35 and a second I/Oswitch 37. The first I/O switch 35 is connected to the three dataregisters 271, 272 and 273, and the first I/O port 281. The second I/Oswitch 37 is connected to the three data registers 271, 272 and 273, andthe second I/O port 282. The first I/O switch 35 and the second I/Oswitch 37 are controlled by a switch controller 33 connected to aninterface controller 25. The register administrator 30 further has a busswitch 31 to schedule data transmission path with the first I/O switch35 and the second I/O switch 37.

[0043]FIG. 7 shows the timing diagram of this embodiment. The tablecontents in row direction represent the data register and the tablecontents in column direction represent processing phase.

[0044] In a first phase, the main frame 20 sends the first data block tothe first data register 271, and the operation is symbolized by H→1B. Atthis time, the second data register 272 and the third data register 273are idle.

[0045] In a second phase, the first data block is moved from the firstdata register 271 to the memory array 291 and the operation issymbolized by 1B→1M. At this time, the main frame 20 sends the seconddata block to the second data register 272, and the operation issymbolized by H→2B. At this time, the third data register 273 is stillidle.

[0046] In a third phase, the second data block is moved from the seconddata register 272 to the second memory array 292, and this operation issymbolized by 2B→2M. At this time, the main frame 20 sends the thirddata block to the third data register 273, and the operation issymbolized by H→3B. At this time, the first data register 271 is idleand this time can be used as writing time of the first memory array 291.

[0047] In a fourth phase, the first data block is moved from the thirddata register 273 to the memory array 291 and the operation issymbolized by 3B→1M. At this time, the main frame 20 sends the firstdata block to the first data register 271, and the operation issymbolized by H→1B. At this time, the second data register 272 is idleand this time can be used as writing time of the second memory array292.

[0048] In a fifth phase, the first data block is moved from the firstdata register 271 to the second memory array 292 and the operation issymbolized by 1B→2M. At this time, the main frame 20 sends the seconddata block to the second data register 272, and the operation issymbolized by H→2B. At this time, the third data register 273 is idleand this time can be used as writing time of the first memory array 291.For the main frame 20 and all data registers, the operations thereof aresimilar to those in the second phase.

[0049] In a sixth phase, the operation in this phase is similar to theoperation in the third phase. In other word, the operations in thesecond to fourth phases are sequentially executed until all data arestored.

[0050] As can be seen from FIG. 7, the main frame 20 has no idle time inall phase of operation even though certain data register is idle in thatphase; the efficiency thereof can be fully exploited.

[0051] Although the present invention has been described with referenceto the preferred embodiment thereof, it will be understood that theinvention is not limited to the details thereof. Various substitutionsand modifications have suggested in the foregoing description, and otherwill occur to those of ordinary skill in the art. Therefore, all suchsubstitutions and modifications are intended to be embraced within thescope of the invention as defined in the appended claims.

We claim:
 1. A memory array apparatus with shorter data accessing time, comprising: a plurality of memory arrays; an interface controller connected to a main frame through a main bus and connected to a micro-controller; a plurality of data registers used to temporarily store data to be accessed; a register administrator having at least one bus switch connected to the main frame through the main bus and connected to the micro-controller, the being controlled by the micro-controller to selectively communicate with one of the data registers; and at least one data I/O port, each data I/O port being connected to all data registers and at least one memory array.
 2. The memory array apparatus with shorter data accessing time as in claim 1, further comprising at least one I/O switch connected to the data registers and each I/O port, respectively, the I/O switch being controller by the micro-controller to selectively communicate with one of the data registers.
 3. The memory array apparatus with shorter data accessing time as in claim 2, further comprising a switch controller connected to the micro-controller, the bus switch and the I/O switch.
 4. The memory array apparatus with shorter data accessing time as in claim 1, wherein the number of the data registers is not less than that of the memory arrays.
 5. A storing method using the memory array apparatus in claim 1 to store data, the method comprising following steps: a. the bus switch of the register administrator is controlled by the micro-controller and selectively switched to a first circuit connected with a first data register; b. storing a first data block of the data to be accessed in a first data register; c. the first data block is moved to the first memory array through the data I/O port, simultaneously, the bus switch of the register administrator is selectively switched to a second circuit connected with a second data register and a second data block of the data to be accessed is stored in a second data register; d. waiting and detecting whether the data stored in the first data register is completely stored in the first memory array; e. the second data block is moved to the second memory array through the data I/O port, simultaneously, the bus switch of the register administrator is selectively switched to the first circuit and a next first data block of the data to be accessed is stored in the first data register; f. waiting and detecting whether the data stored in the second data register is completely stored in the second memory array; and g. repeating steps c to f until all data to be accessed are stored in the memory array.
 6. The storing method as in claim 5, wherein the first data block is stored in the first memory array and the second data block is stored in the second memory array.
 7. A reading method using the memory array apparatus in claim 1 to read data, the method comprising following steps: a. a first data block of the data to be read is moved from the memory arrays to a first data register of the data registers; b. the bus switch of the register administrator is controlled by the micro-controller and selectively switched to a first circuit connected with the first data register; and simultaneously a second data block of the data to be read is moved from the memory arrays to a second data register of the data registers; c. the main frame reads the first data block stored in the first data register through the first circuit; d. waiting and detecting whether the second data block is completely stored in the second data register; e. the bus switch of the register administrator is controlled by the micro-controller and selectively switched to a second circuit connected with the second data register; f. the main frame reads the second data block stored in the second data register through the first circuit; and simultaneously a next first data block of the data to be read is moved from the memory arrays to the first data register; g. waiting and detecting whether the next first data block is completely stored in the first data register; h. repeating steps b to g until all data to be read are accessed by the main frame. 